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ISL5416
TABLE 15. COMMON OUTPUT CONTROL FUNCTIONS (GWA = 0000h) RESET STATE = 0x00000001h
P(31:0)
11
10
9:8
7:0
FUNCTION
CLKO2 POLARITY.
1 = Low to High transition in the middle of data period.
0 = High to Low transition in the middle of data period.
If bit 13 is set:
1 = active high interrupt
0 = active low interrupt.
CLKO1 POLARITY.
1 = Low to High transition in the middle of data period.
0 = High to Low transition in the middle of data period.
HOLD CLKO AFTER RESET.
11 = hold CLKO after hard reset until SYNCIn2.
10 = hold CLKO after hard reset until SYNCIn1. (To re-sync the clock after it has been started, disable it by setting these bits to 00
and then set the bits back to 1X and apply SYNCInX).
01 = enable CLKO after programming this register (This applies only when the CLKO rate is NOT equal to CLKIN rate; there is no
need to align the start if CLKO = CLK, and if that is the case, it starts immediately after programming).
00 = disable CLKO.
CLKO1 RATE.
CLKIN / N for N = 1 to 16.
1 = 0x80h or 0x00h
2 = 0x81h
3 = 0x82h
4 = 0x93h
5 = 0x94h
6 = 0xA5h
7 = 0xA6h
8 = 0xB7h
9 = 0xB8h
10 = 0xC9h
11 = 0xCAh
12 = 0xDBh
13 = 0xDCh
14 = 0xEDh
15 = 0xEEh
16 = 0xFFh
This register (IWA = 0001h) routes the bits from the four
range select blocks to the four nibbles of the Eout bus. Each
nibble of the Eout bus can be controlled by any of the range
selectors. Each range select block contains a mapping table
with three input bits and eight output bits. The three input bits
represent 0 to 42 dB of attenuation in 6 dB steps. The
programming of the input to output bit map depends on the
type of attenuator or VGA used. Typically four bits would be
sufficient for an attenuator while 8 bits might be needed for a
D/A controlled VGA.
33
An example programming for 4 bits per attenuator control is:
0x00001357h
range controls A, B, C, and D control Eout bits 15:12, 11:8,
7:4, 3:0, respectively.
For 8 bits per attenuator control:
0x00000145
range controls A and C control Eout bits 15:8 and 7:0,
respectively.
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